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ADN8831
OSCILLATOR CLOCK FREQUENCY
The ADN8831 has an internal oscillator to generate the switching
frequency for the output stage. This oscillator can be set in either
free-run mode or synchronized to an external clock signal.
Free-Run Operation
The switching frequency is set by a single resistor connected
from FREQ (Pin 13) to ground. Table 5 shows R FREQ for some
common switching frequencies. For free-run operation, connect
SYNCI/SD (Pin 16) and COMPOSC (Pin 17) to PVDD (Pin 18).
Data Sheet
Connecting Multiple ADN8831 Devices
Connecting SYNCO (Pin 15) to the SYNCI/SD pin of another
ADN8831 allows for multiple ADN8831 devices to work
together using a single clock. Multiple ADN8831 devices can be
driven from a single master ADN8831 device, by connecting the
SYNCO pin of the master device to each slave SYNCI/SD pin,
or by daisy-chaining by connecting the SYNCO pin of each
device to the SYNCI/SD pin of the next device. When multiple
ADN8831 devices are clocked at the same frequency, the phase is
to be adjusted to reduce power supply ripple.
Table 5. Switching Frequencies vs. R FREQ
f SWITCH R FREQ
ADN8831
MASTER
COMPOSC
V DD
250 kHz
500 kHz
750 kHz
1 MHz
484 kΩ
249 kΩ
168 kΩ
118 kΩ
FREQ
SYNCI/SD
PHASE
118k ?
V DD
NC
1k ?
Higher switching frequencies reduce the voltage ripple across the
TEC. However, high switching frequencies create more power
dissipation in the external transistors due to the more frequent
charging and discharging of the transistor gate capacitances.
ADN8831
V DD
COMPOSC
SYNCO
10k ?
V DD
ADN8831
SLAVE
COMPOSC
FREQ
1nF
0.1 μ F
1 M ?
R FREQ
FREQ
SYNCI/SD
V DD
SYNCI/SD
PHASE
V PHASE
Figure 13. Free-Run Mode
ADN8831
1nF
External Clock Operation
The switching frequency of the ADN8831 can be synchronized
with an external clock. Connect the clock signal to SYNCI/SD
SLAVE
COMPOSC
FREQ
1k ?
1M ?
0.1 μ F
(Pin 16) and connect COMPOSC (Pin 17) to an R-C network. This
network compensates a PLL to lock on to the external clock.
SYNCI/SD
PHASE
V PHASE
1k ?
ADN8831
COMPOSC
FREQ
SYNCI/SD
1nF
0.1 μ F
1 M ?
EXT. CLOCK
SOURCE
Figure 15. Multiple ADN8831 Devices Driven from a Master Clock
OSCILLATOR CLOCK PHASE
Adjust the oscillator clock phase using a simple resistor divider
at PHASE (Pin 10). Phase adjustment allows two or more
ADN8831 devices to operate from the same clock frequency
and not have all outputs switched simultaneously. This avoids
Figure 14. Synchronize to an External Clock
the potential of an excessive power supply ripple.
To ensure the correct operation of the oscillator, V PHASE is to
remain in the range of 100 mV to 2.4 V. PHASE (Pin 10) is
internally biased at 1.2 V. If PHASE (Pin 10) remains open, the
clock phase is set at 180° as the default.
Rev. A | Page 12 of 20
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